µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
<58>
<59>
Row address
<76>
Column address
Column address
<64>
<61>
<94>
<67>
<77>
<83>
<66>
<95>
<89>
<81>
<63>
UCAS (Output)
LCAS (Output)
<93>
<88>
<95>
RD (Output)
OE (Output)
<102>
<85>
<101>
<85>
<92>
WE (Output)
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
<103>
<87>
<104>
<87>
Data
Data
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
107
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
