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MU9C4480A-12DC 参数 Datasheet PDF下载

MU9C4480A-12DC图片预览
型号: MU9C4480A-12DC
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 4KX64, 85ns, CMOS, PQCC44]
分类和应用: 局域网双倍数据速率静态存储器内存集成电路
文件页数/大小: 28 页 / 143 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C4480A/L  
OPERATIONAL CHARACTERISTICS Continued  
Case  
Internal  
/EC(int)  
Internal  
/MA (int)  
External  
/MI  
Device Select Command Data Write Command Data Read  
Reg.  
Write1  
Read  
1
2
3
1
1
1
X
X
X
X
X
X
DS=FFFFH  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
NO  
YES  
NO  
NO  
YES  
NO  
DS=PA  
DSFFFFH and  
DSPA  
4
5
62  
0
0
0
X
1
0
0
1
1
X
X
X
NO  
NO  
YES3  
NO  
NO  
YES4  
NO5  
NO5  
YES5  
NO  
NO  
YES  
Table 5a: Standard Mode Device Select Response  
Case  
Internal  
/EC(int)  
Internal  
/MA (int)  
External  
/MI  
Device Select  
Reg.  
Command Data Write Command Data Read  
Write1  
Read  
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH  
DS = PA  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
NO  
YES  
NO  
NO  
YES  
NO  
DS FFFFH  
and DS PA  
4
5
62  
0
0
0
0
1
0
0
X
1
X
X
X
YES3,6  
YES3,6  
YES3  
YES4,7  
YES4,7  
YES4  
NO5  
NO5  
YES5  
NO  
NO  
YES  
Table 5b: Enhanced Mode Device Select Response  
NOTES:  
1. Exceptions are:  
A) A write to the Device Select register is always active in all devices;  
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and  
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.  
2. If /MF is disabled in the Control register, /MA (Internal) is forced HIGH preventing a Case 6 response.  
3. This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.  
4. This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.  
5. For a Command Read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain  
(i.e., /FI LOW and /FF HIGH) and NO if it does not.  
6. This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.  
7. This is NO if the Persistent Destination is Memory at Highest-Priority match.  
Memory Access  
THE MEMORY ARRAY  
There are two general ways to get data into and out of the  
memory array: directly or by moving the data through the  
Comparand or mask registers.  
Memory Organization  
The Memory array is organized into 64-bit words with each  
word having an additional two validity bits (Skip and Empty).  
By default, all words are configured to be 64 CAM cells.  
However, bits 8–6 of the Control register can divide each word  
into a CAM field and a RAM field. The RAM field can be  
assigned to the least-significant or most-significant portion  
of each entry. The CAM/RAM partitioning is allowed on 16-  
bit boundaries, permitting selection of the configuration  
shown in Table 8 on page 20, bits 8–6 (e.g., 001 sets the 48  
MSBs to CAM and the 16 LSBs to RAM). Memory Array bits  
designated as RAM can be used to store and retrieve data  
associated with the CAM content at the same memory location.  
The first way, through direct reads or writes, is set up by  
issuing a Set Persistent Destination (SPD) or Set Persistent  
Source (SPS) command. The addresses for the direct access  
can be directly supplied; supplied from the Address register,  
supplied from the Next Free Address register, or supplied as  
the Highest-Priority Match address. Additionally, all the direct  
writes can be masked by either mask register.  
The second way is to move data via the Comparand or mask  
registers. This is accomplished by issuing Data Move  
commands (MOV). Moves using the Comparand register can  
also be masked by either of the mask registers.  
11  
Rev. 3a