Index
Reset timing 2-7, 2-9
synchronous 2-10
ROM, bootstrap iii
X
X-data RAM iii
Y
S
Serial Communication Interface (SCI) iii, 1-1,
1-2, 1-16
Y-data RAM iii
Asynchronous mode timing 2-38
Synchronous mode timing 2-38
signal groupings 1-1
signals 1-1
functional grouping 1-2
Single Data Strobe 1-2
SRAM
read access 2-15
support iv
write access 2-15
Stop mode iv
Stop state
recovery from 2-12
Stop timing 2-7
supply voltage 2-2
Switch mode iii
synchronous bus timings
SRAM
2 wait states 2-26
SRAM 1 wait state (BCR controlled) 2-26
synchronous interrupt from Wait state timing 2-11
synchronous Reset timing 2-10
T
target applications iv
Test Access Port (TAP) iii
timing diagram 2-46
Test Clock (TCLK) input timing diagram 2-45
thermal
design considerations 4-1
Timer
event input restrictions 2-43
Timers 1-1, 1-2, 1-17
interrupt generation 2-43
TQFP 3-1
mechanical drawing 3-9
pin list by name 3-6
pin list by number 3-4
pin-out drawing (bottom) 3-3
pin-out drawing (top) 3-2
W
Wait mode iv
World Wide Web iv
Index-3
MOTOROLA [ MOTOROLA ]
