Index
Host Port Control Register (HPCR) 1-10,
1-12
N
host port
non-multiplexed bus 1-2
non-multiplexed bus timings
read 2-33
configuration 1-9
usage considerations 1-9
Host Port Control Register (HPCR) 1-10, 1-12
Host Request
write 2-34
O
Double 1-2
Single 1-2
off-chip memory iii
OnCE module iii
Host Request (HR) 1-2
Debug request 2-47
I
on-chip DRAM controller iv
On-Chip Emulation (OnCE) module
interface 1-18
information sources iv
instruction cache iii
internal clocks 2-4
interrupt and mode control 1-1, 1-8
interrupt control 1-8
On-Chip Emulation module iii
on-chip memory iii
operating mode select timing 2-11
interrupt timing 2-7
P
external level-sensitive fast 2-10
external negative edge-triggered 2-11
synchronous from Wait state 2-11
package
144-pin TQFP 3-1
196-pin MAP-BGA 3-1
MAP-BGA description 3-10, 3-11, 3-12,
3-15, 3-19
J
Joint Test Action Group (JTAG)
interface 1-18
JTAG iii
TQFP description 3-2, 3-3, 3-4, 3-6, 3-9
Phase-Lock Loop (PLL) 1-1, 2-6
design considerations 4-5
performance issues 4-5
PLL 1-4
JTAG Port
reset timing diagram 2-46
timing 2-46
JTAG/OnCE Interface signals
Debug Event signal (DE signal) 1-18
JTAG/OnCE port 1-1, 1-2
Port A 1-1, 1-5, 2-13
Port B 1-1, 1-2, 1-11
Port C 1-1, 1-2, 1-13
Port D 1-1, 1-2, 1-14
Port E 1-1
M
power 1-1, 1-2, 1-3
power consumption
MAP-BGA 3-1
ball list by name 3-15
ball list by number 3-12
mechanical drawing 3-19
molded array process-ball grid drawing
(bottom) 3-11
design considerations 4-4
power consumption benchmark test A-1
power management iv
program memory expansion iv
program RAM iii
molded array process-ball grid drawing
(top) 3-10
R
maximum ratings 2-1, 2-2
memory expansion port iii
mode control 1-8
recovery from Stop state using IRQA 2-12
reset
Mode select timing 2-7
multiplexed bus 1-2
multiplexed bus timings
read 2-35
clock signals 1-4
interrupt signals 1-8
JTAG signals 1-18
mode control 1-8
write 2-36
OnCE signals 1-18
PLL signals 1-4
Index-2
MOTOROLA [ MOTOROLA ]
