Power Consumption Benchmark
M_TLR0 EQU $FFFF8E
M_TCPR0 EQU $FFFF8D
M_TCR0 EQU $FFFF8C
; TIMER0 Load Reg
; TIMER0 Compare Register
; TIMER0 Count Register
;
Register Addresses Of TIMER1
M_TCSR1 EQU $FFFF8B
M_TLR1 EQU $FFFF8A
M_TCPR1 EQU $FFFF89
M_TCR1 EQU $FFFF88
; TIMER1 Control/Status Register
; TIMER1 Load Reg
; TIMER1 Compare Register
; TIMER1 Count Register
;
Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87
M_TLR2 EQU $FFFF86
M_TCPR2 EQU $FFFF85
M_TCR2 EQU $FFFF84
M_TPLR EQU $FFFF83
M_TPCR EQU $FFFF82
; TIMER2 Control/Status Register
; TIMER2 Load Reg
; TIMER2 Compare Register
; TIMER2 Count Register
; TIMER Prescaler Load Register
; TIMER Prescalar Count Register
;
Timer Control/Status Register Bit Flags
M_TE EQU 0
; Timer Enable
M_TOIE EQU 1
M_TCIE EQU 2
M_TC EQU $F0
M_INV EQU 8
M_TRM EQU 9
M_DIR EQU 11
M_DI EQU 12
M_DO EQU 13
M_PCE EQU 15
M_TOF EQU 20
M_TCF EQU 21
; Timer Overflow Interrupt Enable
; Timer Compare Interrupt Enable
; Timer Control Mask (TC0-TC3)
; Inverter Bit
; Timer Restart Mode
; Direction Bit
; Data Input
; Data Output
; Prescaled Clock Enable
; Timer Overflow Flag
; Timer Compare Flag
;
Timer Prescaler Register Bit Flags
M_PS EQU $600000
M_PS0 EQU 21
M_PS1 EQU 22
; Prescaler Source Mask
;
Timer Control Bits
M_TC0 EQU 4
M_TC1 EQU 5
M_TC2 EQU 6
M_TC3 EQU 7
; Timer Control 0
; Timer Control 1
; Timer Control 2
; Timer Control 3
;------------------------------------------------------------------------
;
;
;
EQUATES for Direct Memory Access (DMA)
;------------------------------------------------------------------------
;
Register Addresses Of DMA
M_DSTR EQU FFFFF4 ; DMA Status Register
M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0
M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1
M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2
M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3
;
Register Addresses Of DMA0
M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register
M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register
M_DCO0 EQU $FFFFED ; DMA0 Counter
M_DCR0 EQU $FFFFEC ; DMA0 Control Register
;
Register Addresses Of DMA1
M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register
M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register
M_DCO1 EQU $FFFFE9 ; DMA1 Counter
M_DCR1 EQU $FFFFE8 ; DMA1 Control Register
;
Register Addresses Of DMA2
M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register
A-8
MOTOROLA [ MOTOROLA ]
