V58C2128(804/404/164)S
Data Strobe Preamble and Postamble Timings for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T4
T0
T1
T2
T3
CK, CK
READ
NOP
NOP
NOP
Command
tRPRE(max)
tRPRE(min)
tRPST(min)
DQS
DQ
tRPST(max)
tDQSQ(min)
D0
D1
tDQSQ(max)
Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
NOP
Read
NOP
Read
NOP
NOP
NOP
NOP
NOP
Command
DQS
A
B
D0 D1 D2 D3 D0 D1 D2 D3
DQ
A
A
A
A
B
B
B
B
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
NOP
Read
NOP
Read
NOP
NOP
NOP
NOP
NOP
Command
DQS
A
B
D0 D1 D2 D3
D0 D1 D2 D3
B B B B
DQ
A
A
A
A
V58C2128(804/404/164)S Rev. 1.6 March 2002
12
MOSEL [ MOSEL VITELIC, CORP ]
