Advance Information
The data streams operate at 2048 kb/s and are Time
Division Multiplexed into 32 identical channels of 64
kb/s bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to parse the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125 µSecond period translating into an 8
kHz frame rate. A valid frame begins when F0i is
MT91L60
logic low coincident with a falling edge of C4i. Refer
to Figure 11 for detailed ST-BUS timing. C4i has a
frequency (4096 kHz) which is twice the data rate.
This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i is also used to
clock the MT91L60 internal functions (i.e., Filter/
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 1
RECEIVE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
DATA 1
TRANSMIT
SCLK
y
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CS
y
Delays due to internal processor timing which are transparent.
The MT91L60:-latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D
7
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
X
X
A
2
A
1
X
X
4 bits - Unused
D
0
A
0
R/W
Figure 5 - Serial Port Relative Timing for Intel Mode 0
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 2
RECEIVE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
DATA 1
TRANSMIT
SCLK
y
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CS
y
Delays due to internal processor timing which are transparent .
The MT91L60:-latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D
7
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
A
2
4 bits - Unused
X
X
R/W
X
A
1
D
0
A
0
X
Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
7-113
MITEL [ MITEL NETWORKS CORPORATION ]
