Advance Information
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.
PWRST/Software Reset (Rst)
While the MT91L60 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing Rst logic low or by setting the PWRST pin.
MT91L60
After Power-up reset (PWRST) or software reset
(Rst) all control bits assume their default states;
µ-Law
functionality, usually 0 dB programmable
gains as well as the device powered up in SSI mode
2048 kb/s operation with Dout tri-stated while there
is no strobe active on STB. If a valid strobe is
supplied to STB, then Dout will be active, during the
defined channel.
To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or put PWRST pin
low.
3V Multi-featured Codec Register Map
00
01
02
03
04
05
06
07
RxINC
-
-
PDFDI
CEN
C
7
D
7
-
RxFG
2
-
-
PDDR
DEN
C
6
D
6
-
RxFG
1
-
-
RST
D8
C
5
D
5
-
RxFG
0
-
-
-
A/µ
C
4
D
4
-
TxINC
-
-
T
x
Mute
Smag/
ITU-T
C
3
D
3
PCM/
ANALOG
TxFG
2
STG
2
-
R
x
Mute
CSL
2
C
2
D
2
loopen
TxFG
1
STG
1
-
T
x
Bsel
CSL
1
C
1
D
1
-
TxFG
0
STG
0
DrGain
R
x
Bsel
CSL
0
C
0
D
0
-
Gain Control
Register 1
Gain Control
Register 2
Path Control
Control
Register 1
Control
Register 2
C-Channel
Register
D-Channel
Register
Loop Back
7-117
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