Advance Information
MT91L60
Pin Description (continued)
Pin #
Name
Description
SOIC DIP
11
12
13
14
13
14
15
17
Dout
Data Output. A high impedance three-state digital output for 8 bit wide channel data
being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with
the rising edge of the bit clock during the timeslot defined by STB, or according to
standard ST-BUS timing.
Din
Data Input. A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit
timeslot used by the device for both transmit and receive data. This active high signal
has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS
mode. CMOS level compatible input.
CLOCKin Clock (Input). (CMOS level compatible). The clock provided to this input pin is used
for the internal device functions. For SSI mode connect the bit clock to this pin when
it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit
clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin.
15
16
17
18
19
20
VDD
Positive Power Supply (Input). Nominally 3 volts.
HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced).
HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker
(balanced).
18
19
22
23
VSSA
M-
Analog Ground (Input). Nominally 0 volts.
Inverting Microphone (Input). Inverting input to microphone amplifier from the
handset microphone.
20
24
M+
NC
Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier
from the handset microphone.
3,9,
No Connect. (DIP Package only).
16,21
7-109
MITEL [ MITEL NETWORKS CORPORATION ]
