MT91L60
Advance Information
An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame
at the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
04 hex or upon encountering the following frames’s
SSI Mode
The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). The frame strobe must be synchronous with,
and eight cycles of, the bit clock. A 4.096 MHz
master clock is also required for SSI operation if the
bit clock is less than 512 kHz. The timing
requirements for SSI are shown in Figures 12 & 13.
FP input, whichever occurs first.
To ensure
D-Channel data integrity, microport read/write
access to Address 04 hex must occur before the
following frame pulse. See Figure 8b for timing.
In SSI mode the MT91L60 supports only B-Channel
operation. The internal C and D Channel registers
used in ST-BUS mode are not functional for SSI
operation. The control bits TxBSel and RxBSel, as
described in the ST-BUS section, are ignored since
the B-Channel timeslot is defined by the input STB
strobe. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.
8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
D-Channel register data is mapped according to
Figure 8c.
CEn - C-Channel
Channel 1 conveys the control/status information for
the Layer
1
transceiver. C-Channel data is
The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.
transferred MSB first on the ST-BUS by the
MT91L60. The full 64 kb/s bandwidth is available
and is assigned according to which transceiver is
being used. Consult the data sheet for the selected
transceiver for its C-Channel bit definitions and order
of bit transfer.
SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
When CEN is high, data written to the C-Channel
register (address 05h) is transmitted, most
significant bit first, on DSTo. On power-up reset
(PWRST) or software reset (Rst, address 03h) all
the
internal
MT91L60
functions
allowing
synchronous operation. If the available bit clock is
128 kHz or 256 kHz, then a 4096 kHz master clock is
required to derive clocks for the internal MT91L60
functions.
C-Channel bits default to logic high.
Receive
C-Channel data (DSTi) is always routed to the read
register regardless of this control bit's logic state.
Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT91L60 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control bits CSL2, CSL1 and CSL0 in Control
Register 2 (address 04h) are used to program the bit
rates.
When low, data transmission is halted and this
timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Filter/Codec and transducer audio paths is selected
on an independent basis for the transmit and receive
paths. TxBSel and RxBSel (Control Register 1,
address 03h) are used for this purpose.
For synchronous operation data is sampled, from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid but PDFDI
and PDDR are not true, then quiet code will be
transmitted on Dout during the valid strobe period.
There is no frame delay through the FDI circuit for
synchronous operation.
If no valid transmit path has been selected then the
timeslot output on DSTo is tri-stated (see PDFDI and
PDDR control bits, Control Register 1 address 03h).
For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
7-116
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