MT90826 CMOS
Advanced Information
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Control Register, CR
Frame Alignment Register, FAR
Input Offset Selection Register 0, DOS0
Input Offset Selection Register 1, DOS1
Input Offset Selection Register 2, DOS2
Input Offset Selection Register 3, DOS3
Input Offset Selection Register 4, DOS4
Input Offset Selection Register 5, DOS5
Input Offset Selection Register 6, DOS6
Input Offset Selection Register 7, DOS7
Frame Output Offset Register, FOR0
Frame Output Offset Register, FOR1
Frame Output Offset Register, FOR2
Frame Output Offset Register, FOR3
Unused
Unused
Unused
Bit Error Input Selection Register, BISR
Bit Error Count Register, BECR
Table 3 - Address Map for Registers (A13 = 0)
Stream Address (ST0-31)
Channel Address (Ch0-255)
Stream
Location
Channel
Location
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
1
1
1
1
1
.
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
0
0
0
1
.
0
0
0
0
1
1
1
1
0
.
0
0
1
1
0
0
1
1
0
.
0
1
0
1
0
1
0
1
0
.
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
.
.
.
.
.
.
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
0
0
.
0
0
1
1
.
0
0
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
0
1
0
1
.
Ch 62
Ch 63 (Note 3)
Ch 64
Ch 65
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Stream 22
Stream 23
Stream 24
Stream 25
Stream 26
Stream 27
Stream 28
Stream 29
Stream 30
Stream 31
.
Ch 126
Ch 127 (Note 4)
Ch 128
Ch 129
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Ch 254
Ch 255 (Note 5)
1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4Mb/s
4. Channels 0 to 127 are used when serial stream is at 8Mb/s
5. Channels 0 to 255 are used when serial stream is at 16Mb/s
Table 4 - Address Map for Memory Locations (A13 = 1)
10
MITEL [ MITEL NETWORKS CORPORATION ]
