MT9076
Preliminary Information
Bit
Name
Functional Description
7
RAI
AIS
Remote Alarm Indication. This bit is set to one in the event of receipt of a remote alarm,
i.e. A(RAI) = 1. It is cleared when the register is read.
6
5
4
3
2
1
0
Alarm Indication Signal. This bit is set to one in the event of receipt of an all ones alarm.
It is cleared when the register is read.
AIS16
LOS
AIS Time Slot 16 Alarm. This bit is set to one in the event of receipt of an all ones alarm
in the time slot 16. It is cleared when the register is read.
Loss of Signal. This bit is set to one in the event of loss of received signal. It is cleared
when the register is read.
AUXP
Auxiliary Alarm. This bit is set to one in the event of receipt of the auxiliary alarm pattern.
It is cleared when the register is read.
MFALM Multiframe Alarm. This bit is set to one in the event of receipt of a multiframe alarm. It is
cleared when the register is read.
RSLIP
- - -
Received Slip. This bit is set to one in the event of receive elastic buffer slip. It is cleared
when the register is read.
Unused.
Table 136 - Alarm Reporting Latch
(Page 4, Address 12H) (E1)
Bit
Name
Functional Description
7 - 0
EFAS7 - 0 Errored FAS Counter. An 8 bit counter that is incremented once for every receive
frame alignment signal that contains one or more errors.
Table 137 - Errored Frame Alignment Signal Counter
(Page 4, Address 13H) (E1)
Bit
Name
Functional Description
1-0
EC15-8
E bit Error Counter. The most significant bits of the E bit error counter.
Table 138 - E-bit Error Counter
(Page 4, Address 14H) (E1)
Bit
Name
Functional Description
7 - 0
EC7-0
E bit Error Counter. The least significant 8 bits of the E-bit error counter.
Table 139 - E-bit Error Counter
(Page 4, Address 15H) (E1)
Bit
Name
Functional Description
7 - 0 LCV15 - 8 Most Significant Bits of the LCV Counter. The most significant eight bits of a 16 bit
counter that is incremented once for every line code violation received. A line code is
defined as a bipolar violation that is not a part of HDB3 encoding where the control bit
EXZ is set low. Where EXZ is set high a violation is defined as either a non-HDB3 bipolar
violation or an occurrance of excess zeros.
Table 140 - Most Significant Bits of the LCV Counter
(Page 4, Address 16H) (E1)
118
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