MT9076
Preliminary Information
Bit
Name
Functional Description
7
FERRO
Errored Framing Alignment Signal Counter Overflow Interrupt. When unmasked this
interrupt bit goes high whenever the errored frame alignment signal counter changes from
FFH to 00H. Reading this register clears this bit.
6
CRCO
CRC Error Counter Overflow Interrupt. When unmasked this interrupt bit goes high
whenever the CRC error counter changes from FFH to 00H. Reading this register clears
this bit.
5
4
- - -
Unused
FEBEO
E-bit Counter Overflow Interrupt. When unmasked this interrupt bit goes high whenever
the E-bit counter changes from FFH to 00H. Reading this register clears this bit.
3
2
1
0
LCVO
Line Code Violation Counter Overflow Interrupt. When unmasked this interrupt bit goes
high whenever the line code violation counter changes from FFH to 00H. Reading this
register clears this bit.
PRBSO
Pseudo Random Bit Sequence Error Counter Overflow Interrupt. When unmasked
this interrupt bit goes high whenever the PRBS error counter changes from FFH to 00H.
Reading this register clears this bit.
PRBSMFO Pseudo Random Bit Sequence Multiframe Counter Counter Overflow Interrupt.
When unmasked this interrupt bit goes high whenever the multiframe counter attached to
the PRBS error counter overflows. FFH to 00H. 1 - unmasked, 0 - masked.
SaI
Sa Bit Interrupt. When unmasked this interrupt goes high whenever either a change of
state of any of the received Sa bits Sa5, Sa6, Sa7 or Sa8 (SaBorNi = 1) or a change of
state of any of the received Sa nibbles (SaBorNi = 0). The control bit SaBorNi is located in
page 1 address 12H bit 4.
Table 146 - Interrupt Word Two
(Page 4, Address 1DH) (E1)
122
MITEL [ MITEL NETWORKS CORPORATION ]
