Preliminary Information
MT9076
21.0 Master Status 2 (Page-4)
21.1
Master Status 2 (Page 04H) (E1)
Address
Register
Function
(A4A3A2A1A0)
10H (Table 134) PRBS Error Counter
11H (Table 135) CRC Multiframe counter for PRBS
12H (Table 136) Alarm Reporting Latch
13H (Table 137) Framing Bit Counter
14H (Table 138) E-bit Error Counter Ebt
15H (Table 139) E-bit Error Counter Ebt
PS7-0
PSM7-0
RAI, AIS, AIS16, LOS, AUXP, MFALM, RSLIP
EFAS7-0
EC15-EC8
EC7-EC0
16H (Table 140) Most Significant Line Code Violation Error LCV15 - LCV8
Counter
17H (Table 141) Least Significant Line Code Violation Error LCV7 - LCV0
Counter
18H (Table 142) CRC- 4 Error Counter CEt
19H (Table 143) CRC- 4 Error Counter CEt
1AH
CC15-CC8
CC7 - CC0
Unused.
1BH (Table 144) Interrupt Word Zero
TFSYNI, MFSYNI, CRCSYNI,AISI, LOSI,
CEFI,YI, RxSLPI
1CH (Table 145) Interrupt Word One
1DH (Table 146) Interrupt Word Two
1EH (Table 147) Interrupt Word Three
1FH (Table 148) Overflow Reporting Latch
FERRI, CRCERRI, EBITI, AIS16I, LCVI,
PRBSERRI, AUXPI, RAII,
FERRO,CRCO,FEBEO,LCVO,PRBSO,PRBSM
FO, SaI
HDLC0I,HDLC1I,HDLC2,JAI,1SECI,5SECI,RC
RI,SIGI
FERROL,CRCOL,FEBEOL,LCVOL, PRBSOL,
PRBSMFOL
Table 133 - Master Status 2 (Page 4) (E1)
Bit
Name
Functional Description
7 - 0
PS7-0
This counter is incremented for each PRBS error detected on any of the receive channels
connected to the PRBS error detector.
Table 134 - PRBS Error Counter
(Page 4, Address 10H) (E1)
Bit
Name
Functional Description
7 - 0
PSM7-0 This counter is incremented for each received CRC multiframe. It is cleared when the
PRBS Error Counter is written to.
Table 135 - CRC Multiframe Counter for PRBS
(Page 4, Address 11H) (E1)
117
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