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MT9076AP 参数 Datasheet PDF下载

MT9076AP图片预览
型号: MT9076AP
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1 3.3V单芯片收发器 [T1/E1/J1 3.3V Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 160 页 / 413 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Preliminary Information  
MT9076  
Bit  
Name  
Functional Description  
7
ESF  
Extended Super Frame. Setting this bit enables transmission and reception of the 24 frame  
superframe DS1 protocol.  
6
5
SLC96 SLC96 Mode Select. Setting this bit enables input and output of the Fs bit pattern on the TxDL  
and RxDL pins. Frame synchronization is the same as in the case of D4 operation. The  
transmitter will insert A and B bits every 6 frames after synchronizing to the Fs pattern clocked  
into Txdl. Receive Fs bits are not monitored for the Framing Bit Error Counter.  
CXC  
Cross Check. Setting this bit in ESF mode enables a cross check of the CRC-6 remainder  
before the frame synchronizer pulls into sync. This process adds at least 6 milliseconds to the  
frame synchronization time. Setting this bit in D4 (not ESF) mode enables a check of the Fs  
bits in addition to the Ft bits during frame synchronization  
4 - 3 RS1- 0 Reframe Select 1 - 0. These bits set the criteria for an automatic reframe in the event of  
framing bits errors. The combinations available are:  
RS1 - 0, RS0 - 0 = sliding window of 2 errors out of 4.  
RS1 - 0, RS0 - 1 = sliding window of 2 errors out of 5.  
RS1 - 1, RS0 - 0 = sliding window of 2 errors out of 6.  
RS1 - 1, RS0 - 1 = no reframes due to framing bit errors.  
2
FSI  
Fs Bit Include. Only applicable in D4 mode (not ESF or SLC96). Setting this bit causes  
errored Fs bits to be included as framing bit errors. A bad Fs bit will increment the Framing  
Error Bit Counter, and will potentially cause a reframe (if it is the second bad framing bit out of  
5). The Fs bit of the receive frame 12 will only be included if D4SECY is set.  
1
0
ReFR  
Reframe. A low - to - high transition on this bit causes an automatic reframe.  
MFReFR MultiFrame Reframe. Only applicable in D4 or SLC96 mode. A low - to - high transition on this  
bit causes an automatic multiframe reframe. The signaling bits are frozen until multiframe  
synchronization is achieved. Terminal frame synchronization is not affected.  
Table 21 - Framing Mode Select (T1)  
(Page 1, Address 10H)  
59  
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