Preliminary Information
MT9076
17.0 Detected Events
17.1
T1 mode
17.1.1 Severely Errored Frame Event
In T1 mode, bit 5 page 3H address 10H toggles whenever a sliding window detects 2 framing errors events (Ft or
ESF) in a sliding window of 6.
17.1.2 Loop Code Detect
T1.403 defines SF mode line loopback activate and deactivate codes. These codes are either a framed or un-
framed repeating bit sequence of 00001 for activation or 001 for deactivation. The standard goes on to say that
these codes will persist for five seconds or more before the loopback action is taken. In T1 mode MT9076 will
detect both framed and unframed line activate and de-activate codes even in the presence of a BER of 3 x 10-
3. Line Loopback Disable Detect - LLDD - in the Alarm Status Word (bit 0 address 11H of page 3H) will be
asserted when a repeating 001 pattern (either framed or unframed) has persisted for 48 milliseconds. Line
Loopback Enable Detect LLED in the Alarm Status Word will be asserted when a repeating 00001 pattern
(either framed or unframed) has persisted for 48 milliseconds.
17.1.3 Pulse Density Violation Detect
In T1 mode, bit 2 of address 11H on page 3H (PDV) toggles if the receive data fails to meet ones density
requirements. It will toggle upon detection of 16 consecutive zeros on the line data, or if there are less than N
ones in a window of 8(N+1) bits - where N = 1 to 23.
17.1.4 Timer Outputs
In T1 mode, MT9076 has a one second timer derived from the 20 Mhz oscillator pins. The timer may be used to
trigger interrupts for T1.403/408 performance messaging.
17.2
E1 mode
17.2.1 Consecutive Frame Alignment Patterns (CONFAP)
Two consecutive frame alignment signals in error.
17.2.2 Receive Frame Alignment Signals
These bits are received on the PCM 30 and link in bit positions two to eight of time slot 0 - frame alignment
signal. These signals form the frame alignment signal and should be 0011011.
17.2.3 Receive Non Frame Alignment Signal
This signal is received on the PCM 30 and link in bit position two of time slot 0 - non frame alignment signal.
17.2.4 Receive Multiframe Alignment Signals
These signal are received on the PCM 30 and link in bit position one to four of time slot 16 of frame zero of
every signaling multiframe.
18.0 Interrupts
The MT9076 has an extensive suite of maskable interrupts, which are divided into four categories based on the
type of event that caused the interrupt. Each interrupt has an associated mask and interrupt bit. When an
unmasked interrupt event occurs, IRQ will go low and one or more bits of the appropriate interrupt register will
go high(T1/E1). After each interrupt register is read it is automatically cleared. When all interrupt registers are
cleared IRQ will return to a high impedance state. This function can also be accomplished by toggling the INTA
bit (page 1, address 1AH.)
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MITEL [ MITEL NETWORKS CORPORATION ]
