ISO-CMOS MT8950
125 µs
C2i
INPUT
F1i
INTERNAL
ENABLE
DSTo
7
7
6
6
5
5
2
2
1
1
4
4
3
3
0
HIGH IMPEDANCE
7
7
6
6
OUTPUT
DSTi/
CSTi
INPUTS
0
CA
Figure 11 - Timing Diagram - 125 µs Frame Period
90%
50%
10%
C2i
Input
tCR
tCF
90%
10%
F1i, CA
Input
tEF
tER
tES
tEH
High
Impedance
DSTo
Output
tPLZ
tPZH
Figure 12 - Timing Diagram - ST-BUS Interface Enable
90%
50%
10%
C2i
Input
tCR
tCF
90%
50%
10%
DSTo
Output
tOR
tOF
tPHL
tPLH
90%
50%
10%
DSTi, CSTi
Input
tIF
tIH
tIR
tISH
tISL
Figure 13 - Timing Diagram - ST-BUS Input/Output
6-17