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MH89760BS 参数 Datasheet PDF下载

MH89760BS图片预览
型号: MH89760BS
PDF下载: 下载PDF文件 查看货源
内容描述: ST- BUS⑩系列T1 / ESF成帧器和接口的初步信息 [ST-BUS⑩ FAMILY T1/ESF Framer & Interface Preliminary Information]
分类和应用: 电信集成电路光电二极管
文件页数/大小: 38 页 / 848 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MH89760B  
Preliminary Information  
The channel assignment circuit is therefore very  
simple.  
communications. The basic mode of transmission is  
to assemble data into packets (e.g., HDLC or  
ethernet) which are transported on a T1 link  
configured as a 1.536 Mbit/s serial channel. No T1  
repeaters are required if the transmission link length  
is 1300 ft. or less (e.g., business complex or  
university). However, if the transmission link length is  
greater than 1300 ft., a repeatered T1 line must be  
leased from the local telephone operating company.  
The switch matrix, in the message mode, passes  
monitor and control information between the  
microprocessor and the T1 interface over ST-BUS  
stream 0. The MT8980 is also used to reformat the  
ST-BUS data streams between the protocol  
converter and the MH89760B interface.  
Figure 17 is divided into three functional blocks  
which are the protocol converter, switch matrix, and  
T1 interface. The protocol section is dependent on  
the particular format that is chosen. In this example it  
is assumed that the protocol is HDLC. The Transmit  
Clock Enable (TxCEN) and the Receive Clock  
Enable (RxCEN) of the MT8952 are active for a  
period of 24 consecutive ST-BUS channels, and the  
clock speed is 2.048 MHz. This enables the protocol  
conversion section to interface directly to the switch  
matrix. The switch matrix switches the first 24  
channels received from the protocol section into the  
24 valid timeslots used by the MH89760B. Once the  
data enters the T1 interface the MH89760B formats  
and transmits the data on the T1 line.  
The MH89760B and the MT8941 form the T1  
interface. The MH89760B converts the data received  
on the ST-BUS into a 1.544 MHz T1 stream. All of  
the formatting and decoding of the T1 signal is  
performed by this device. The MT8941 provides the  
clock synchronization required to operate in a loop  
timed mode. Digital phase-locked loop #2 provides  
ST-BUS clocks that are synchronized to the  
extracted 8kHz, and digital phase-locked loop #1  
provides the transmit 1.544 MHz clock synchronized  
to the ST-BUS.  
7. High Speed Data Transmission Link  
High speed data links are becoming increasingly  
popular in private networks and computer  
Protocol Converter  
Switch Matrix  
T1 Interface  
MT8952  
MT8980  
MH89760B  
CDSTo  
CDSTi  
TxCEN  
DSTi  
OUTA  
STi0  
STo0  
STo1  
STi1  
EQUAL-  
IZER  
DSTo  
OUTB  
RxT  
STo2  
STi2  
CSTi1  
CSTo  
RxCEN  
STo3  
CSTi0  
RxR  
C2i  
F0i  
C4i  
F0i  
F0i  
C4i  
E8Ko  
C1.5i  
MT8941  
DPLL #1  
CVb  
F0i  
C1.5i  
12.352  
MHz Osc.  
C12i  
MICRO  
DPLL #2  
F0b  
F0i  
C8Kb  
C16i  
C4b  
C20  
C4i  
C2i  
16.384  
MHz Osc.  
Figure 17 - High Speed Data Transmission Link  
4-78  
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