ProASIC3 Flash Family FPGAs
Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
VMV (V)
2.5 V LVCMOS
2.5
1.8
1.5
3.3
3.3
–
–
–
–
–
5.14
2.13
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
1.48
18.13
18.13
3.3 V PCI-X
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
Static Power
PDC2 (mW) 1
Dynamic Power
PAC9 (µW/MHz) 2
VMV (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range3
2.5 V LVCMOS
3.3
3.3
2.5
1.8
1.5
–
–
–
–
–
17.24
17.24
5.19
1.8 V LVCMOS
2.18
1.5 V LVCMOS (JESD8-11)
Notes:
1.52
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Revision 18
2-8
MICROSEMI [ Microsemi ]
