ProASIC3 Flash Family FPGAs
Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings 1
Applicable to Standard I/O Banks
Static Power
PDC3 (mW) 2
Dynamic Power
CLOAD (pF)
VCCI (V)
PAC10 (µW/MHz) 3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range4
2.5 V LVCMOS
35
35
35
35
35
3.3
3.3
2.5
1.8
1.5
–
–
–
–
–
431.08
431.08
247.36
128.46
89.46
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2.
3.
P
is the static power (where applicable) measured on VCCI.
is the total dynamic power measured on VCC and VCCI.
DC3
P
AC10
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 18
2-10
MICROSEMI [ Microsemi ]
