128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
2. Without latching A[MAX:17] in the asynchronous READ cycle, the previously latched
A[MAX:17] applies.
Asynchronous WRITE Cycles
Table 56: AADM Asynchronous Write Timings
Symbol
tPHWL
tELWL
MIN (ns)
150
0
tWLWH
tDVWH
tWHEH
tWHDX
tWHWL
tVPWH
tWVVL
tBHWH
tWHGL
tGHWL
40
40
0
0
20
200
0
200
0
0
1. A READ cycle may be restarted prior to completing a pending READ operation, but this
may occur only once before the sense operation is allowed to complete.
2. tVHQV applies to asynchronous read access time.
Notes:
Figure 53: AADM Asynchronous WRITE Cycle (Latching A[MAX:0])
t
WHDX
A[MAX:16]
A[15:0]
DQ[15:0]
A/DQ[15:0]
ADV#
t
WHEH
CE#
OE#
t
t
t
DVWH
ELWL
GHWL
t
WHGL
t
t
t
ELWL
WLWH
WHWL
WE#
t
BHWH
WP#
RST#
t
PHWL
1. CE# need not be de-asserted at beginning of cycle if OE# does not have output control.
Note:
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128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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