128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
Figure 56: AADM Synchronous Burst READ Cycle (ADV# Not De-asserted Between Address Cycles)
A[MAX:16]
AVCH
A[15:0]
AVCH
DQ[15:0]
DQ[15:0]
A
A/DQ[15:0]
CLK
t
t
Latency count
t
t
t
CHAX
CHAX
t
CHQX
CHQV
t
CHVL
t
t
t
CHVH
VLCH
ADV#
CE#
ELCH
t
GHCH
t
t
t
GLCH
CHGH
CHGL
OE#
WE#
t
t
t
CHTV
CHTX
GLTV
t
GLTX
WAIT
1. CE# need not be de-asserted at beginning of cycle if OE# does not have output control.
2. Diagram shows WAIT as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
3. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown).
Notes:
Figure 57: AADM Synchronous Burst READ Cycle (Latching A[15:0] only)
A[15:0]
DQ[15:0]
DQ[15:0]
A
A/DQ[15:0]
CLK
Latency count
tCHQV
tCHAX
tAVCH
tCHVL
tCHQX
tVLCH
tCHVH
ADV#
CE#
tELCH
tCHGL
OE#
WE#
tCHTV
tCHTX
tGLTV
tGLTX
WAIT
1. Diagram shows WAIT as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
2. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown).
Notes:
3. Without latching A[MAX:16] in the synchronous READ cycle, the previously latched
A[MAX:16] applies.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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