128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
Figure 54: AADM Asynchronous WRITE Cycle (Latching A[15:0] only)
t
WHDX
A[15:0]
DQ[15:0]
A/DQ[15:0]
ADV#
t
WHEH
CE#
OE#
t
t
DVWH
ELWL
t
WHGL
t
t
t
ELWL
WLWH
WHWL
WE#
t
BHWH
WP#
RST#
t
PHWL
1. Without latching A[MAX:16] in the WRITE cycle, the previously latched A[MAX:16] ap-
plies.
Note:
Synchronous READ and WRITE Cycles
Just as asynchronous bus cycles, synchronous bus cycles (RCR[15] = 0b) can have one or
two address cycles. If the are two address cycles, the upper address must be latched first
with OE# at VIL followed by the lower address with OE# at VIH. If there is only one ad-
dress cycle, only the lower address will be latched and the previously latched upper ad-
dress applies. For reads, sensing begins when the lower address is latched, but for syn-
chronous reads, addresses are latched on a rising clock CLK instead of a rising ADV#
edge.
For synchronous bus cycles with two address cycles, it is not necessary to de-assert
ADV# between the two address cycles. This allows both the upper and lower address to
be latched in only two clock periods.
Synchronous READ Cycles
For synchronous READ operation, the specifications in the AADM Asynchronous and
Latching Timings Table also apply.
Table 57: AADM Synchronous Timings
Target (104 MHz)
Target (104 MHz)
Max (ns)
Symbol
tCLK
Min (ns)
Notes
9
tRISE/tFALL
tAVCH
tVLCH
1.5
6
3
3
tELCH
3.5
tCHQV
tCHQX
tCHAX
7
2
5
5
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