128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
In asynchronous mode (RCR[15] = 1b), WAIT always indicates valid data when driven.
In synchronous mode (RCR[15] = 0b), WAIT indicates valid data only after the latency
count has lapsed and the data output data is truly valid.
Asynchronous READ and WRITE Cycles
For asynchronous READ and WRITE cycles, ADV# must be toggled HIGH-LOW-HIGH a
minimum of one time and a maximum of two times during a bus cycle. If ADV# is tog-
gled LOW twice during a bus cycle, OE# must be held LOW for the first ADV# rising edge
and OE# must be held HIGH for the second ADV# rising edge. The first ADV# rising edge
(with OE# LOW) captures A[MAX:16]. The second ADV# rising edge (with OE# HIGH)
captures A[16:1]. Each bus cycle must toggle ADV# HIGH-LOW-HIGH at least one time
in order to capture A[16:1]. For asynchronous reads, sensing begins when the lower ad-
dress is latched.
During asynchronous cycles, it is optional to capture A[MAX:17]. If these addresses are
not captured, then the previously captured A[MAX:17] contents will be used.
Asynchronous READ Cycles
For AADM, note that asynchronous read access is from the rising edge of ADV# rather
than the falling edge (tVHQV rather than tVLQV).
Table 55: AADM Asynchronous and Latching Timings
Symbol
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
MIN (ns)
MAX (ns)
20
Notes
150
0
0
9
9
0
7
tEHEL
tELTV
11
9
tEHTZ
tGLTV
tGLTX
tGHTZ
tAVVH
tELVH
tVLVH
tVHVL
tVHAX
tVHGL
tVHQV
tPHVH
7
0
9
5
9
7
7
5
3
96
1
30
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