128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
Table 55: AADM Asynchronous and Latching Timings (Continued)
Symbol
tGHVH
tGLVH
MIN (ns)
MAX (ns)
Notes
3
3
3
tVHGH
1. A READ cycle may be restarted prior to completing a pending READ operation, but this
may occur only once before the sense operation is allowed to complete.
2. tVHQV applies to asynchronous read access time.
Notes:
Figure 51: AADM Asynchronous READ Cycle (Latching A[MAX:0])
A[MAX:16]
A[15:0]
t
DQ[15:0]
A/DQ[15:0]
ADV#
t
t
t
AVVH
VHAX
AVVH
t
VHAX
t
t
t
VLVH
VHVL
VLVH
VHQV
t
EHQZ
t
t
ELVH
t
EHEL
CE#
OE#
t
GHQZ
t
GLQX
GLQV
t
t
t
t
t
t
GLVH VHGH
GHVH
VHGL
GHVH + VHGL
t
t
GLTV
GLTX
GHTZ
t
t
EHTZ
WAIT
1. CE# need not be de-asserted at beginning of the cycle if OE# does not have output con-
trol.
Notes:
2. Diagram shows WAIT as active LOW (RCR[10] = 0).
Figure 52: AADM Asynchronous READ Cycle (Latching A[15:0] only)
A[15:0]
tAVVH
DQ[15:0]
A/DQ[15:0]
ADV#
tVHAX
tVLVH
tVHQV
tEHQZ
tEHEL
tELVH
CE#
OE#
tGHQZ
tGLQX
tGLQV
tVHGL
tVHGH + tGHVL
tGLTV
tGLTX
tGHTZ
tEHTZ
WAIT
1. Diagram shows WAIT as active LOW (RCR[10] = 0).
Notes:
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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