128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
AADM Mode
AADM Feature Overview
The following is a list of general requirements for AADM mode.
Feature availability. AADM mode is available in devices that are configured as A/D
MUX. With this configuration, AADM mode is enabled by setting a specific volatile bit in
the read configuration register.
High-address capture (A[MAX:17]). When AADM mode is enabled, A[MAX:17] and
A[16:1] are captured from the A/ DQ[15:0] balls. The selection of A[MAX:17] or A[16:1] is
determined by the state of the OE# input, as A[MAX:17] is captured when OE# is at VIL.
READ and WRITE cycle support. In AADM mode, both asynchronous and synchronous
cycles are supported.
Customer requirements. For AADM operation, the customer is required to ground
A[MAX:17].
Other characteristics. For AADM, all other device characteristics (program time, erase
time, ICCS, etc.) are the same as A/D MUX unless otherwise stated.
AADM Mode Enable (RCR[4] = 1)
Setting RCR[4] to its non-default state (1b) enables AADM mode. The default device
configuration upon reset or power-up is A/D MUX mode. Upon setting RCR[4] = 1, the
upper addresses, A[MAX:17] are latched. All 0s are latched by default.
Bus Cycles and Address Capture
AADM bus operations have one or two address cycles. For two address cycles, the upper
address (A[MAX:17]) must be issued first, followed by the lower address (A[16:1]). For
bus operations with only one address cycle, only the lower address is issued. The upper
address that applies is the one that was most recently latched on a previous bus cycle.
For all READ cycles, sensing begins when the lower address is latched, regardless of
whether there are one or two address cycles.
In bus cycles, the external signal that distinguishes the upper address from the lower
address is OE#. When OE# is at VIH, a lower address is captured; when OE# is at VIL, an
upper address is captured.
When the bus cycle has only one address cycle, the timing waveform is similar to A/D
MUX mode. The lower address is latched when OE# is at VIH, and data is subsequently
outputted after the falling edge of OE#.
When the device initially enters AADM mode, the upper address is internally latched as
all 0s.
WAIT Behavior
The WAIT behavior in AADM mode functions the same as the legacy non-MUX WAIT
behavior (A/D MUX WAIT behavior is unique). In other words, WAIT will always be
driven whenever DQ[15:0] is driven, and WAIT will tri-state whenever DQ[15:0] tri-state.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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