128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AADM Mode
Table 57: AADM Synchronous Timings (Continued)
Target (104 MHz)
Min (ns)
Target (104 MHz)
Max (ns)
Symbol
tCHTV
tCHVL
tCHTX
tCHVH
tCHGL
tVLVH
tVHCH
tCHGH
tGHCH
tGLCH
Notes
7
2.5
2
2
2.5
tCLK
3
4, 5
3, 4
2 × tCLK
2
2
3
1. In synchronous burst READ cycles, the asynchronous OE# to ADV# setup and hold times
must also be met (tGHVH and tVHGL) to signify that the address capture phase of the
bus cycle is complete.
Notes:
2. A READ cycle may only be terminated (prior to the completion of sensing data) one time
before a full bus cycle must be allowed to complete.
3. The device must operate down to 9.6 MHz in synchronous burst mode.
4. During the address capture phase of a read burst bus cycle, OE# timings relative to CLK
shall be identical to those of ADV# relative to CLK.
5. To prevent A/D bus contention between the host and the memory device, OE# may only
be asserted LOW after the host has satisfied the ADDR hold spec, tCHAX.
6. Rise and fall time specified between VIL and VIH.
Figure 55: AADM Synchronous Burst READ Cycle (ADV# De-asserted Between Address Cycles)
A[MAX:16]
A[15:0]
t
DQ[15:0]
DQ[15:0]
A
A/DQ[15:0]
CLK
Latency count
t
t
t
CHAX
AVCH
t
CHAX
t
t
AVCH
CHQX
CHQV
t
VLCH
VLCH
t
t
CHVL
t
CHVL
t
t
CHVH
CHVH
ADV#
CE#
ELCH
t
t
t
t
GLCH
CHGH
GHCH
CHGL
OE#
WE#
t
t
t
CHTV
CHTX
GLTV
t
GLTX
WAIT
1. CE# need not be de-asserted at beginning of cycle if OE# does not have output control.
2. Diagram shows WAIT as active LOW (RCR[10] = 0) and asserted with data (RCR[8] = 0).
3. For no-wrap bursts, end-of-wordline WAIT states could occur (not shown).
Notes:
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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