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N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
READ IDENTIFICATION Operations  
READ IDENTIFICATION Operations  
READ ID and MULTIPLE I/O READ ID Commands  
To execute the READ ID or MULTIPLE I/O READ ID commands, S# is driven LOW and  
the command code is input on DQn. The device outputs the information shown in the  
tables below. If an ERASE or PROGRAM cycle is in progress when the command is exe-  
cuted, the command is not decoded and the command cycle in progress is not affected.  
When S# is driven HIGH, the device goes to standby. The operation is terminated by  
driving S# HIGH at any time during data output.  
Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands  
Unique ID  
is Output  
Command Name  
READ ID  
Data In  
DQ0  
Data Out  
DQ0  
Extended  
Yes  
Dual  
No  
Quad  
No  
Yes  
No  
MULTIPLE I/O READ ID  
DQ[3:0]  
DQ[1:0]  
No  
Yes  
Yes  
1. Yes in the protocol columns indicates that the command is supported and has the same  
functionality and command sequence as other commands marked Yes.  
Note:  
Table 21: Read ID Data Out  
Size  
(Bytes) Name  
Content Value  
Assigned by  
1
2
Manufacturer ID  
Device ID  
20h  
JEDEC  
Memory Type  
BAh  
Manufacturer  
Factory  
Memory Capacity  
Unique ID  
20h (512Mb)  
17  
1 Byte: Length of data to follow  
10h  
2 Bytes: Extended device ID and device  
configuration information  
ID and information such as uniform  
architecture, and HOLD  
or RESET functionality  
14 Bytes: Customized factory data  
Optional  
1. The 17 bytes of information in the unique ID is read by the READ ID command, but can-  
not be read by the MULTIPLE I/O READ ID command.  
Note:  
Table 22: Extended Device ID, First Byte  
Bit 7  
Bit 6  
Reserved 1 = Alternate BP Volatile configuration  
Bit 51  
Bit 42  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
HOLD#/RESET#:  
0 = HOLD  
Addressing:  
0 = by byte  
Architecture:  
00 = Uniform  
scheme  
0 = Standard BP  
scheme  
register bit setting:  
0 = Micron XIP  
1 = Basic XIP  
1 = RESET  
1. For alternate BP scheme information, contact the factory.  
2. For more information, contact the factory.  
Notes:  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
39  
© 2011 Micron Technology, Inc. All rights reserved.  
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