512Mb, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
Figure 12: WRITE LOCK REGISTER Command
Extended
0
7
8
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQ[0]
Command
MSB
A[MAX]
MSB
Dual
0
3
4
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DIN
DIN
DQ[1:0]
Command
MSB
A[MAX]
MSB
Quad
0
1
2
Cx
C
LSB
A[MIN]
LSB
DIN
DIN
DIN
DQ[3:0]
Command
MSB
A[MAX]
MSB
1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1).
For dual SPI protocol, Cx = 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, Cx = 1 + ((A[MAX] + 1)/4).
Note:
CLEAR FLAG STATUS REGISTER Command
To execute the CLEAR FLAG STATUS REGISTER command and clear the error bits
(erase, program, and protection), S# is driven LOW. For extended SPI protocol, the com-
mand code is input on DQ0. For dual SPI protocol, the command code is input on
DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation
is terminated by driving S# HIGH at any time.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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