512Mb, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
Figure 11: READ LOCK REGISTER Command
Extended
0
7
8
Cx
C
LSB
A[MIN]
DQ[0]
DQ1
Command
High-Z
MSB
A[MAX]
LSB
DOUT
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Dual
0
3
4
Cx
C
LSB
A[MIN]
LSB
DOUT DOUT
DOUT
MSB
DOUT
DOUT
DQ[1:0]
Command
MSB
A[MAX]
Quad
0
1
2
Cx
C
LSB
A[MIN]
LSB
DOUT
DOUT
MSB
DOUT
DQ[3:0]
Command
Don’t Care
MSB
A[MAX]
1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1).
For dual SPI protocol, Cx = 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, Cx = 1 + ((A[MAX] + 1)/4).
Note:
WRITE LOCK REGISTER Command
To initiate the WRITE LOCK REGISTER command, the WRITE ENABLE command must
be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until
the eighth bit of the last data byte has been latched in, after which it must be driven
HIGH. The command code is input on DQn, followed by address bytes that point to a
location in the sector, and then one data byte that contains the desired settings for lock
register bits 0 and 1.
When execution is complete, the write enable latch bit is cleared within tSHSL2 and no
error bits are set. Because lock register bits are volatile, change to the bits is immediate.
WRITE LOCK REGISTER can be executed when an ERASE SUSPEND operation is in ef-
fect. After the data is latched in, S# must be driven HIGH.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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