512Mb, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
followed by the data bytes. For dual SPI protocol, the command code is input on
DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input
on DQ[3:0], followed by the data bytes.
Because register bits are volatile, change to the bits is immediate. After the data is latch-
ed in, S# must be driven HIGH. Reserved bits are not affected by this command.
WRITE EXTENDED ADDRESS REGISTER Command
To initiate a WRITE EXTENDED ADDRESS REGISTER command, the WRITE ENABLE
command must be executed to set the write enable latch bit to 1.
Note: The WRITE ENABLE command must not be executed for part numbers
N25Q512A83GSF40X and N25Q512A83G1240X.
S# is driven LOW and held LOW until the eighth bit of the last data byte has been latch-
ed in, after which it must be driven HIGH. The command code is input on DQ0, fol-
lowed by the data bytes. For dual SPI protocol, the command code is input on DQ[1:0],
followed by the data bytes. For quad SPI protocol, the command code is input on
DQ[3:0], followed by the data bytes.
Because register bits are volatile, change to the bits is immediate. After the data is latch-
ed in, S# must be driven HIGH. Reserved bits are not affected by this command.
READ LOCK REGISTER Command
To execute the READ LOCK REGISTER command, S# is driven LOW. For extended SPI
protocol, the command code is input on DQ0, followed by address bytes that point to a
location in the sector. For dual SPI protocol, the command code is input on DQ[1:0]. For
quad SPI protocol, the command code is input on DQ[3:0]. Each address bit is latched
in during the rising edge of the clock. For extended SPI protocol, data is shifted out on
DQ1 at a maximum frequency fC during the falling edge of the clock. For dual SPI proto-
col, data is shifted out on DQ[1:0], and for qual SPI protocol, data is shifted out on
DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data out-
put.
When the register is read continuously, the same byte is output repeatedly. Any READ
LOCK REGISTER command that is executed while an ERASE, PROGRAM, or WRITE cy-
cle is in progress is rejected with no affect on the cycle in progress.
Table 19: Lock Register
Note 1 applies to entire table
Bit
7:2
1
Name
Settings
Description
Reserved
0
Bit values are 0.
Write lock down 0 = Cleared (Default)
1 = Set
Volatile bit: the device always powers-up with this bit cleared, which
means sector lock down and sector write lock bits can be set.
When this bit set, neither of the lock register bits can be written to
until the next power cycle.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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