512Mb, Multiple I/O Serial Flash Memory
READ IDENTIFICATION Operations
Table 24: Parameter ID (Continued)
Byte
Address
512Mb
Data
Description
Bits
0
Supports FAST READ operation in dual SPI protocol
40h
1
Reserved
3:1
111b
1
Supports FAST READ operation in quad SPI protocol
4
Reserved
Reserved
Reserved
7:5
111b
FFFFFFh
FFFFh
00111b
43:41h
45:44h
46h
FFFFFFh
FFFFh
4:0
Number of dummy clock cycles required before valid output from
FAST READ operation in dual SPI protocol
Number of XIP confirmation bits for FAST READ operation in dual SPI
protocol
7:5
001b
Command code for FAST READ operation in dual SPI protocol
Reserved
47h
49:48h
4Ah
7:0
FFFFh
4:0
BBh
FFFFh
01001b
Number of dummy clock cycles required before valid output from
FAST READ operation in quad SPI protocol
Number of XIP confirmation bits for FAST READ operation in quad
SPI protocol
7:5
001b
Command code for FAST READ operation in quad SPI protocol
Sector type 1 size (4k)
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
EBh
0Ch
20h
10h
D8h
00h
00h
00h
00h
Sector type 1 command code (4k)
Sector type 2 size (64KB)
Sector type 2 command code 64KB)
Sector type 3 size (not present)
Sector type 3 size (not present)
Sector type 4 size (not present)
Sector type 4 size (not present)
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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