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N25Q512A13GF840E 参数 Datasheet PDF下载

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型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
READ IDENTIFICATION Operations  
Table 24: Parameter ID (Continued)  
Description  
Byte  
Address  
512Mb  
Data  
Bits  
Supports DUAL OUTPUT FAST READ operation (single input address,  
dual output)  
32h  
0
1
Number of address bytes used (3-byte or 4-byte) for array READ,  
WRITE, and ERASE commands  
2:1  
01b  
Supports double transfer rate clocking  
3
4
1
1
Supports DUAL INPUT/OUTPUT FAST READ operation (dual input ad-  
dress, dual output)  
Supports QUAD INPUT/OUTPUT FAST READ operation (quad input  
address, quad output)  
5
6
1
1
Supports QUAD OUTPUT FAST READ operation (single input address,  
quad output)  
Reserved  
7
1
FFh  
Reserved  
33h  
34h  
35h  
36h  
37h  
38h  
7:0  
7:0  
7:0  
7:0  
7:0  
4:0  
Flash size (bits)  
FFh  
FFh  
FFh  
1Fh  
Number of dummy clock cycles required before valid output from  
QUAD INPUT/OUTPUT FAST READ operation  
01001b  
Number of XIP confirmation bits for QUAD INPUT/OUTPUT FAST  
READ operation  
7:5  
001b  
Command code for QUAD INPUT/OUTPUT FAST READ operation  
39h  
3Ah  
7:0  
4:0  
EBh  
Number of dummy clock cycles required before valid output from  
QUAD OUTPUT FAST READ operation  
00111b  
Number of XIP confirmation bits for QUAD OUTPUT FAST READ op-  
eration  
7:5  
001b  
Command code for QUAD OUTPUT FAST READ operation  
3Bh  
3Ch  
7:0  
4:0  
6Bh  
Number of dummy clock cycles required before valid output from  
DUAL OUTPUT FAST READ operation  
00111b  
Number of XIP confirmation bits for DUAL OUTPUT FAST READ oper-  
ation  
7:5  
001b  
Command code for DUAL OUTPUT FAST READ operation  
3Dh  
3Eh  
7:0  
4:0  
3Bh  
Number of dummy clock cycles required before valid output from  
DUAL INPUT/OUTPUT FAST READ operation  
00111b  
Number of XIP confirmation bits for DUAL INPUT/OUTPUT FAST  
READ  
7:5  
7:0  
001b  
BBh  
Command code for DUAL INPUT/OUTPUT FAST READ operation  
3Fh  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
42  
© 2011 Micron Technology, Inc. All rights reserved.  
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