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N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
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内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
READ REGISTER and WRITE REGISTER Operations  
Figure 10: WRITE REGISTER Command  
Extended  
0
7
8
9
10  
11  
12  
13  
14  
15  
C
LSB  
LSB  
DIN  
MSB  
DIN  
DIN  
DIN  
DIN  
DIN  
DIN  
DIN  
DIN  
DIN  
DIN  
DQ0  
Command  
MSB  
MSB  
MSB  
Dual  
0
3
4
5
6
7
C
LSB  
LSB  
DIN  
MSB  
DIN  
DIN  
DIN  
DQ[1:0]  
Command  
0
Quad  
1
2
3
C
LSB  
LSB  
DIN  
MSB  
DIN  
DQ[3:0]  
Command  
1. Supports all WRITE REGISTER commands except WRITE LOCK REGISTER.  
Notes:  
2. A WRITE NONVOLATILE CONFIGURATION REGISTER operation requires data being sent  
starting from least significant byte. For this command, the data in consists of two bytes.  
WRITE NONVOLATILE CONFIGURATION REGISTER Command  
To execute the WRITE NONVOLATILE CONFIGURATION REGISTER command, the  
WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is  
driven LOW and held LOW until the 16th bit of the last data byte has been latched in,  
after which it must be driven HIGH. For extended SPI protocol, the command code is  
input on DQ0, followed by two data bytes. For dual SPI protocol, the command code is  
input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code  
is input on DQ[3:0], followed by the data bytes. When S# is driven HIGH, the operation,  
which is self-timed, is initiated; its duration is tWNVCR.  
When the operation is in progress, the program or erase controller bit of the flag status  
register is set to 0. To obtain the operation status, the flag status register must be polled  
twice, with S# toggled twice in between commands. When the operation completes, the  
program or erase controller bit is cleared to 1. The end of operation can be detected  
when the flag status register outputs the program or erase controller bit to 1 both times.  
When the maximum time achieved (see AC Characteristics and Operating Conditions),  
polling the flag status register twice is not required.  
WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command  
To execute a WRITE VOLATILE CONFIGURATION REGISTER command or a WRITE  
ENHANCED VOLATILE CONFIGURATION REGISTER command, the WRITE ENABLE  
command must be executed to set the write enable latch bit to 1. S# is driven LOW and  
held LOW until the eighth bit of the last data byte has been latched in, after which it  
must be driven HIGH. For extended SPI protocol, the command code is input on DQ0,  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
34  
© 2011 Micron Technology, Inc. All rights reserved.  
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