512Mb, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
READ EXTENDED ADDRESS REGISTER Command
To initiate a READ EXTENDED ADDRESS REGISTER command, S# is driven LOW. For
extended SPI protocol, the command code is input on DQ0, and output on DQ1. For
dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For
quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0].
The operation is terminated by driving S# HIGH at any time during data output.
When the register is read continuously, the same byte is output repeatedly.
WRITE STATUS REGISTER Command
To issue a WRITE STATUS REGISTER command, the WRITE ENABLE command must be
executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the
eighth bit of the last data byte has been latched in, after which it must be driven HIGH.
For extended SPI protocol, the command code is input on DQ0, followed by the data
bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the da-
ta bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the
data bytes. When S# is driven HIGH, the operation, which is self-timed, is initiated; its
duration is tW.
This command is used to write new values to status register bits 7:2, enabling software
data protection. The status register can also be combined with the W#/VPP signal to
provide hardware data protection. The WRITE STATUS REGISTER command has no ef-
fect on status register bits 1:0.
When the operation is in progress, the program or erase controller bit of the flag status
register is set to 0. To obtain the operation status, the flag status register must be polled
twice, with S# toggled twice in between commands. When the operation completes, the
program or erase controller bit is cleared to 1. The end of operation can be detected
when the flag status register outputs the program or erase controller bit to 1 both times.
When the maximum time achieved (see AC Characteristics and Operating Conditions),
polling the flag status register twice is not required.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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