欢迎访问ic37.com |
会员登录 免费注册
发布采购

N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号N25Q512A13GF840E的Datasheet PDF文件第27页浏览型号N25Q512A13GF840E的Datasheet PDF文件第28页浏览型号N25Q512A13GF840E的Datasheet PDF文件第29页浏览型号N25Q512A13GF840E的Datasheet PDF文件第30页浏览型号N25Q512A13GF840E的Datasheet PDF文件第32页浏览型号N25Q512A13GF840E的Datasheet PDF文件第33页浏览型号N25Q512A13GF840E的Datasheet PDF文件第34页浏览型号N25Q512A13GF840E的Datasheet PDF文件第35页  
512Mb, Multiple I/O Serial Flash Memory  
READ REGISTER and WRITE REGISTER Operations  
READ REGISTER and WRITE REGISTER Operations  
READ STATUS REGISTER or FLAG STATUS REGISTER Command  
To initiate a READ STATUS REGISTER command, S# is driven LOW. For extended SPI  
protocol, the command code is input on DQ0, and output on DQ1. For dual SPI proto-  
col, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI proto-  
col, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is  
terminated by driving S# HIGH at any time during data output.  
The status register can be read continuously and at any time, including during a PRO-  
GRAM, ERASE, or WRITE operation.  
The flag status register can be read continuously and at any time, including during an  
ERASE or WRITE operation.  
If one of these operations is in progress, checking the write in progress bit or program or  
erase controller bit is recommended before executing the command.  
The flag status register must be read any time a PROGRAM, ERASE, or SUSPEND/  
RESUME command is issued, or after a RESET command while device is busy. The cycle  
is not complete until bit 7 of the flag status register outputs 1. Refer to Command Defi-  
nitions for more information.  
The end of operations such as power-up,WRITE STATUS REGISTER, and WRITE NON-  
VOLATILE CONFIGURATION REGISTER can be detected by means of a READ FLAG STA-  
TUS REGISTER command being issued twice to poll the flag status register for both die,  
S# toggled between command execution, and bit 7 of the flag status register outputs 1  
both times.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
31  
© 2011 Micron Technology, Inc. All rights reserved.  
 复制成功!