512Mb, Multiple I/O Serial Flash Memory
Command Definitions
14. Requires the READ FLAG STATUS REGISTER command being issued with at least one byte
output. (After code, at least 8 clock pulses in extended SPI, 4 clock pulses in dual I/O SPI,
and 2 clock pulses in quad I/O SPI.) The cycle is not complete until bit 7 of the flag status
register outputs 1.
15. The end of operation can be detected by means of a READ FLAG STATUS REGISTER com-
mand being issued twice, S# toggled between command execution, and bit 7 of the flag
status register outputs 1 both times.
16. The WRITE ENABLE command must be issued first before this command can be execu-
ted. Not necessary for part numbers N25Q512A83GSF40x and N25Q512A83G1240x.
17. Only available for part numbers N25Q512A83GSF40x and N25Q512A83G1240x.
18. The code 38h is valid only for part numbers N25Q512A83GSF40x and
N25Q512A83G1240x; the code 12h is valid for the other part numbers.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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