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N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
Command Definitions  
Table 18: Command Set (Continued)  
Note 1 applies to entire table  
Dual  
I/O  
Quad  
I/O  
Data  
Bytes  
Command  
Code  
D8h  
DCh  
C4h  
C7h  
7Ah  
75h  
Extended  
Notes  
4, 13, 14  
SECTOR ERASE  
Yes  
Yes  
Yes  
0
4-BYTE SECTOR ERASE  
DIE ERASE  
4, 13, 14, 17  
4, 13, 14  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
0
0
0
BULK ERASE  
13, 14, 17  
2, 13, 14  
PROGRAM/ERASE RESUME  
PROGRAM/ERASE SUSPEND  
ONE-TIME PROGRAMMABLE (OTP) Operations  
READ OTP ARRAY  
4Bh  
42h  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
1 to 64  
5
PROGRAM OTP ARRAY  
4-BYTE ADDRESS MODE Operations  
ENTER 4-BYTE ADDRESS MODE  
EXIT 4-BYTE ADDRESS MODE  
QUAD Operations  
4, 13, 14  
B7h  
E9h  
0
0
2, 16  
ENTER QUAD  
35h  
F5h  
2, 17  
2, 17  
EXIT QUAD  
1. Yes in the protocol columns indicates that the command is supported and has the same  
functionality and command sequence as other commands marked Yes.  
Notes:  
2. Address bytes = 0. Dummy clock cycles = 0.  
3. Address bytes = 3. Dummy clock cycles default = 8.  
4. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles = 0.  
5. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-  
fault = 8. Dummy clock cycles default = 10 (when quad SPI protocol is enabled). Dummy  
clock cycles are configurable by the user.  
6. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-  
fault = 6. Dummy clock cycles default = 8 when quad SPI protocol is enabled. Dummy  
clock cycles are configurable by the user.  
7. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-  
fault = 8. Dummy clock cycles are configurable by the user.  
8. Address bytes = 4. Dummy clock cycles = 0.  
9. Address bytes = 4. Dummy clock cycles default = 8. Dummy clock cycles default = 10  
(when quad SPI protocol is enabled). Dummy clock cycles are configurable by the user.  
10. Address bytes = 4. Dummy clock cycles default = 10. Dummy clock cycles is configurable  
by the user.  
11. When the device is in dual SPI protocol, the command can be entered with any of these  
three codes. The different codes enable compatibility between dual SPI and extended  
SPI protocols.  
12. When the device is in quad SPI protocol, the command can be entered with any of these  
three codes. The different codes enable compatibility between quad SPI and extended  
SPI protocols.  
13. The WRITE ENABLE command must be issued first before this command can be execu-  
ted.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
29  
© 2011 Micron Technology, Inc. All rights reserved.  
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