‡
Pre lim in a ry
MT9V012 - 1/6-In ch VGA CMOS Dig it a l Im a g e Se n so r
Re g ist e rs
In Table 6, the “Bad Frame” column shows where changing a register or register field
will cause a bad frame. The following notation is used:
• N—No. Changing the register value will not produce a bad frame.
• Y—Yes. Changing the register value might produce a bad frame.
• YM—Yes; but the bad frame will be masked out unless the “show bad frames” feature
(Reg0x0D[8])is enabled.
Ch a n g e s t o In t e g ra t io n Tim e
If the integration time (Reg0x09) is changed while FRAME_VALID is asserted for frame
N, the first frame output using the new integration time is frame (N + 2). The sequence is
as follows:
1. During fram e N, the new integration time is held in the Reg0x09 pending register.
2. At the start of frame (N + 1), the new integration time is transferred to the Reg0x09 live
register. Integration for each row of frame (N + 1) has been completed using the old
integration time.
3. The earliest time that a row can start integrating using the new integration time is
immediately after that row has been read for frame (N + 1). The actual time that rows
start integrating using the new integration time is dependent upon the new value of
the integration time.
4. When frame (N + 1) is read out, it will have been integrated using the new integration
time.
If the integration time is changed (Reg0x09 written) on successive frames, each value
written will be applied for a single frame; the latency between writing a value and it
affecting the frame readout remains at two frames.
Ch a n g e s t o Ga in Se t t in g s
Usually, when the gain settings (Reg0x2B, Reg0x2C, Reg0x2D, Reg0x2E, and Reg0x2F)
are changed, the gain is updated on the next frame start. When the integration time and
the gain are changed at the same time, the gain update is held off by one frame so that
the first frame output with the new integration time also has the new gain applied.
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
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