‡
Pre lim in a ry
MT9V012 - 1/6-In ch VGA CMOS Dig it a l Im a g e Se n so r
Re g ist e rs
Ta b le 6: Re g ist e r De scrip t io n (co n t in u e d )
Syn c’d
De fa u lt t o Fra m e
Ba d
Fra m e
Bit
Bit De scrip t io n
(h e x)
St a rt
7:6
0
Y
YM
Zoom
In zoom mode, the pixel data rate is slowed by a factor of
either two or four, and either 1 or 3 additional blank rows
are added between output rows. This is designed to give the
controller logic time to repeat data to fill in a window—that
is either two or four times larger—with repeated data.
The pixel clock speed is not affected by this operation, and
the output data for each pixel is valid for either two or four
pixel clocks. In zoom 2x mode, every row is followed by a
blank row (with its own LINE_VALID, but all data bits = 0) of
equal time. In zoom 4x mode, every row is followed by three
blank rows. The combination of this register and an
appropriate change to the window-sizing registers enables
the user to zoom to a region of interest without affecting
the frame rate.
00 = no zoom (default).
X1 = zoom 2x.
10 = zoom 4x.
8
9
0
0
Y
N
YM
Y
Over-Sized
When this bit is set, a four-pixel border will be output
around the active image array, independent of readout
mode (skip, zoom, mirror, etc.). Setting this bit adds 8 to the
number of rows and columns in the frame.
Show Border
This bit indicates whether to show the border enabled by bit
8.
X0 = normal behavior, no border.
01 = border is enabled but not shown; vertical blanking is
increased by 8 rows, horizontal blanking is increased by 8
pixels.
11 = border is enabled and shown; FRAME_VALID time is
extended by 8 rows, LINE_VALID is extended by 8 pixels. See
“Pixel Border” on page 32.
10
14
1
0
Y
N
YM
N
Use 1 ADC—
Context B
The MT9V012 operates with a single ADC, so this read-only
bit always reads 1.
Continuous
LINE_VALID
1 = Continuous LINE_VALID (continue producing LINE_VALID
during vertical blanking).
0 = Normal LINE_VALID (default, no LINE_VALID during
vertical blanking).
15
0
1
N
Y
N
XOR LINE_VALID 1 = LINE_VALID = continuous LINE_VALID XOR
FRAME_VALID.
0 = LINE_VALID determined by bit 9.
Ineffective if continuous LINE_VALID is set.
0x21 (33) Re a d Mo d e - Co n t e xt A
2
YM
Row Skip 2x—
Context A
When read mode for context A is selected (Reg0xC8[3] = 0):
1 = read out two rows, skip two rows (i.e. row 8, row 9, row
12, row 13…).
0 = normal readout.
3
1
1
Y
Y
YM
N
Column Skip
2x—Context A
When read mode for context A is selected (Reg0xC8[3] = 0):
1 = read out 2 columns, skip 2 columns (as with rows).
0 = normal readout.
10
1 ADC Mode—
Context A
The MT9V012 operates with a single ADC, so this read-only
bit always reads 1.
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
26
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