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MT58L64L32F 参数 Datasheet PDF下载

MT58L64L32F图片预览
型号: MT58L64L32F
PDF下载: 下载PDF文件 查看货源
内容描述: 2MB : 128K ×18 , 64K X 32/36流通型SyncBurst SRAM [2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM]
分类和应用: 静态存储器
文件页数/大小: 24 页 / 481 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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2Mb: 128K x 18, 64K x 32/36  
FLOW-THROUGH SYNCBURST SRAM  
TRUTH TABLE  
OPERATION  
ADDRESS CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE#  
USED  
CLK  
DQ  
Deselected Cycle, Power-Down  
Deselected Cycle, Power-Down  
Deselected Cycle, Power-Down  
Deselected Cycle, Power-Down  
Deselected Cycle, Power-Down  
SNOOZE MODE, Power-Down  
READ Cycle, Begin Burst  
None  
H
X
X
H
X
H
X
L
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H  
L-H  
L-H  
L-H  
L-H  
X
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Q
None  
L
L
L
None  
L
X
L
L
None  
L
H
H
X
L
None  
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None  
X
L
X
X
X
L
External  
External  
External  
External  
External  
Next  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
READ Cycle, Begin Burst  
L
L
L
H
X
L
High-Z  
D
WRITE Cycle, Begin Burst  
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
READ Cycle, Begin Burst  
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst  
L
L
L
H
L
High-Z  
Q
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next  
L
H
L
High-Z  
Q
Next  
L
Next  
L
H
X
X
L
High-Z  
D
Next  
L
Next  
L
L
D
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z  
Q
H
X
X
High-Z  
D
L
D
NOTE: 1. X means Dont Care.# means active LOW. H means logic HIGH. L means logic LOW.  
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#) and BWE# are LOW or  
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.  
3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc  
pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions.  
DQPc and DQPd are only available on the x36 version.  
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.  
5. Wait states are inserted by suspending burst.  
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held  
HIGH throughout the input data hold time.  
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.  
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more  
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing  
diagram for clarification.  
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM  
MT58L128L18F_2.p65 Rev. 6/01  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000,MicronTechnology,Inc.  
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