2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
PIN ASSIGNMENT (Top View)
100-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
SA
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
NC/SA*
SA
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
ADV#
ADSP#
ADSC#
OE#
SA
SA
SA
SA
BWE#
GW#
CLK
SA
DNU
DNU
V
SS
DD
V
V
DD
SS
V
x18
CE2#
BWa#
BWb#
NC
DNU
DNU
SA0
SA1
SA
NC
CE2
CE#
SA
SA
SA
SA
SA
100
MODE
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
NC/SA*
SA
SA
ADV#
ADSP#
ADSC#
OE#
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SA
SA
SA
SA
BWE#
GW#
SA
DNU
DNU
CLK
V
SS
DD
V
V
DD
SS
V
x32/x36
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
DNU
DNU
SA0
SA1
SA
SA
CE#
SA
SA
SA
SA
100
MODE
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*Pin 50 is reserved for address expansion.
**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 6/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000,MicronTechnology,Inc.
4
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