2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V)
-6.8
-7.5
-8.5
-10
DESCRIPTION
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Clock
Clock cycle time
Clock frequency
Clock HIGH time
t
KC
KF
8.0
8.8
10.0
15
ns
MHz
ns
f
125
6.8
113
7.5
100
8.5
66
t
KH
1.8
1.8
1.9
1.9
1.9
1.9
4.0
4.0
2
2
t
Clock LOW time
KL
ns
Output Times
t
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
KQ
10.0
ns
ns
ns
ns
ns
ns
ns
t
KQX
KQLZ
KQHZ
OEQ
OELZ
OEHZ
1.5
1.5
1.5
1.5
3.0
1.5
3.0
1.5
3
t
3, 4, 5, 6
3, 4, 5, 6
7
3, 4, 5, 6
3, 4, 5, 6
t
3.8
3.8
4.2
4.2
5.0
5.0
5.0
5.0
t
t
0
0
0
0
t
3.8
4.2
5.0
5.0
t
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
AS
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
ADSS
t
AAS
WS
t
Byte write enables
(BWa#-BWd#, GW#, BWE#)
t
Data-in
Chip enable (CE#)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
DS
1.8
1.8
2.0
2.0
2.0
2.0
2.5
2.5
ns
ns
8, 9
8, 9
t
CES
t
AH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
ADSH
t
AAH
t
Byte write enables
WH
(BWa#-BWd#, GW#, BWE#)
t
Data-in
Chip enable (CE#)
DH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 9
8, 9
t
CEH
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) and
Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V).
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured 500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW for the required setup and hold times. A WRITE
cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 6/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000,MicronTechnology,Inc.
12
MICRON [ MICRON TECHNOLOGY ]
