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MT48LC8M8A2 参数 Datasheet PDF下载

MT48LC8M8A2图片预览
型号: MT48LC8M8A2
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 55 页 / 1456 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb : x4, x8, x16  
SDRAM  
Co m m a n d s  
Tru th Tab le 1 p rovid es a q u ick referen ce of  
available com m ands. This is followed by a written de-  
scription of each com m and. Three additional Truth  
Tables appear following the Operation section; these  
tables provide current state/ next state inform ation.  
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION  
(Note: 1)  
NAME (FUNCTION)  
CS# RAS# CAS# WE# DQM ADDR  
DQs NOTES  
COMMAND INHIBIT (NOP)  
H
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
NO OPERATION (NOP)  
X
ACTIVE (Select bank and activate row)  
READ (Select bank and column, and start READ burst)  
WRITE (Select bank and column, and start WRITE burst)  
BURST TERMINATE  
X
Bank/Row  
Bank/Col  
X
X
3
4
4
8
8
H
H
H
L
L/H  
L/H  
X
L
Bank/Col Valid  
H
H
L
L
X
Code  
X
Active  
PRECHARGE (Deactivate row in bank or banks)  
L
X
X
X
5
AUTO REFRESH or SELF REFRESH  
(Enter self refresh mode)  
L
H
X
6, 7  
LOAD MODE REGISTER  
L
L
L
L
X
L
Op-Code  
X
2
8
8
Write Enable/Output Enable  
Write Inhibit/Output High-Z  
Active  
High-Z  
H
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.  
2. A0-A11 define the op-code written to the mode register.  
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.  
4. A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) provide column address; A10 (HIGH) enables the auto precharge feature  
(nonpersistent), while A10 (LOW) disables the auto precharge feature; BA0, BA1 determine which bank is being read  
from or written to.  
5. A10 (LOW): BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Dont  
Care.”  
6. This command is AUTO REFRESH if CKE is (HIGH), SELF REFRESH if CKE is LOW.  
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Dont Care” except for CKE.  
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).  
64Mb: x4, x8, x16 SDRAM  
64MSDRAM_F.p65 – Rev. F; Pub. 1/03  
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.  
©2003, Micron Technology, Inc.  
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