64Mb : x4, x8, x16
SDRAM
CAS La t e n cy
Op e ra t in g Mo d e
The CAS latency is the delay, in clock cycles, be-
tween the registration of a READ com m and and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
The norm al operating m ode is selected by setting
M7 and M8 to zero; the other com binations of values for
M7 and M8 are reserved for future use and/ or test
m odes. The program m ed burst length applies to both
READ and WRITE bursts.
Test m odes and reserved states should not be used
because unknown operation or incom patibility with
future versions m ay result.
If a READ com m and is registered at clock edge n,
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access tim es are m et, the data will be
valid by clock edge n + m. For exam ple, assum ing that
the clock cycle tim e is such that all relevant access tim es
are m et, if a READ com m and is registered at T0 and the
latency is program m ed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 indicates the operating fre-
quencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown
op eration or in com p atibility with fu tu re version s
m ay result.
Writ e Bu rst Mo d e
When M9 = 0, the burst length program m ed via
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, th e p rogram m ed bu rst len gth ap p lies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
Ta b le 2
CAS La t e n cy
ALLOWABLE OPERATING
FREQUENCY (MHz)
Fig u re 2
CAS La t e n cy
CAS
CAS
SPEED
-6
LATENCY = 2
LATENCY = 3
T0
T1
T2
T3
–
£ 166
£ 143
£ 133
£ 125
CLK
-7E
£ 133
£ 100
£ 100
COMMAND
READ
NOP
t
NOP
t
-75
LZ
OH
-8E
D
OUT
DQ
t
AC
CAS Latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
10
MICRON [ MICRON TECHNOLOGY ]
