64Mb: x32
SDRAM
SELFREFRESHMODE
T0
T1
T2
Tn + 1
To + 1
To + 2
( (
) )
( (
) )
t
CL
CLK
CKE
t
( (
) )
( (
) )
t
CK
CH
t
> t
RAS
CKS
( (
) )
( (
) )
( (
) )
t
t
CKS
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
DQM 0-3
PRECHARGE
NOP
NOP
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9
A10
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
BA0, BA1
DQ
BANK(S)
High-Z
( (
) )
( (
) )
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
UNDEFINED
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
1
1.5
1
ns
ns
ns
ns
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
CMH
CMS
RAS
1
CL
2
1.5
1.5
42
18
70
2
t
CK (3)
CK (2)
CK (1)
5
38.7 120,000
120,000
42
20
70
120,000
ns
ns
ns
t
t
10
10
RP
15
55
t
20
20
XSR
*CAS latency indicated in parentheses.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
40
MICRON [ MICRON TECHNOLOGY ]
