64Mb: x32
SDRAM
INITIALIZEANDLOADMODEREGISTER
T0
T1
Tn + 1
To + 1
CL
Tp + 1
Tp + 2
Tp + 3
( (
) )
( (
) )
( (
) )
t
t
CK
CLK
CKE
((
))
t
( (
) )
( (
) )
( (
) )
CH
t
t
CKH
CKS
((
))
((
))
( (
) )
( (
) )
( (
) )
( (
) )
t
t
t
t
t
t
CMS CMH
CMS CMH
CMS CMH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
LOAD MODE
REGISTER
COMMAND
DQM 0-3
NOP
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CODE
ROW
ROW
BANK
A0-A9
A10
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
CODE
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
ALL
BANKS
CODE
BA0, BA1
DQ
High-Z
((
))
((
))
T = 100µs
(MIN)
t
t
t
t
MRD
RP
RFC
RFC
Power-up:
Program Mode Register 1, 2, 5
AUTO REFRESH
VDD and
AUTO REFRESH
Precharge
all banks
CK stable
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
1
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
1
1.5
1
1
1.5
1
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
CH
2.75
2.75
7
CMH
CMS
MRD
RFC
1
CL
2
1.5
2
1.5
2
2
t
t
CLK (3)
CLK (2)
CLK (1)
5
2
CK
t
t
10
10
60
15
60
18
70
20
ns
ns
20
20
RP
*CAS latency indicated in parentheses.
NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. Outputs are guaranteed High-Z after command is issued.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
36
MICRON [ MICRON TECHNOLOGY ]
