64Mb: x32
SDRAM
ALTERNATING BANK READ ACCESSES 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
DQM 0-3
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS
CMH
t
AS
t
AH
2
2
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
A0-A9
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
AS
t
AH
BANK 0
BANK 0
BANK 4
t
BANK 4
BA0, BA1
BANK 0
t
AC
t
t
AC
t
AC
AC
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
DOUT
m
D
OUT m + 1
D
OUT m + 2
D
OUT m + 3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
t
RP - BANK 0
RCD - BANK 0
CAS Latency - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 4
CAS Latency - BANK 4
RRD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
1
MAX
MIN
2
MAX UNITS
t
t
AC (3)
4.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
1
ns
ns
ns
ns
ns
t
t
t
t
AC (2)
-
-
7.5
CMH
CMS
1
t
AC (1)
17
17
1.5
1
1.5
1
2
t
AH
AS
1
1.5
2
1
1.5
2.5
2.5
6
1
2
LZ
1
t
t
t
t
OH
1.5
2
2.5
42
70
20
20
14
t
CH
2.75
2.75
7
RAS
RC
38.7 120,000
42
60
18
18
12
120,000
120,000
ns
ns
ns
ns
ns
t
t
t
CL
2
55
15
15
10
t
CK (3)
CK (2)
CK (1)
5
RCD
t
t
t
-
10
20
1
10
20
1
RP
t
-
RRD
CKH
1.5
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
44
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