64Mb: x32
SDRAM
POWER-DOWN MODE 1
T0
T1
T2
Tn + 1
Tn + 2
( (
) )
t
CK
t
CL
CLK
CKE
( (
t
CH
) )
t
t
CKS
CKS
( (
) )
t
t
CKS
CKH
t
t
CMS CMH
PRECHARGE
( (
) )
COMMAND
DQM 0-3
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
SINGLE BANK
t
AS
t
AH
( (
) )
( (
) )
BANK
BA0, BA1
DQ
BANK(S)
High-Z
( (
) )
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
20
MAX
MIN
20
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
CK (1)
ns
ns
ns
ns
ns
t
t
t
t
1.5
2.5
2.5
6
2
CKH
CKS
1
1.5
1
1
t
t
t
CH
2.75
2.75
7
1.5
1
2
CL
2
CMH
CMS
1
t
CK (3)
CK (2)
5
1.5
1.5
2
t
10
10
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
37
MICRON [ MICRON TECHNOLOGY ]
