64Mb: x32
SDRAM
AUTOREFRESHMODE
T0
T1
T2
Tn + 1
CL
To + 1
( (
) )
( (
) )
t
CLK
CKE
t
t
( (
( (
CK
CH
) )
) )
( (
) )
( (
) )
t
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
DQM 0–3
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
( (
) )
) )
( (
) )
( (
) )
( (
( (
) )
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0–A9
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
BANK(S)
BA0, BA1
DQ
BANK
( (
( (
) )
) )
High-Z
( (
) )
( (
) )
t
t
t
RP
RFC
RFC
Precharge all
active banks
DON’T CARE
UNDEFINED
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
1
1.5
1
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
CMH
CMS
RFC
1
CL
2
1.5
60
15
1.5
60
2
t
CK (3)
CK (2)
CK (1)
5
70
20
t
t
10
10
RP
18
20
20
*CAS latency indicated in parentheses.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
39
MICRON [ MICRON TECHNOLOGY ]
